Method for forming a semiconductor connection with a top surface having an enlarged recess

ABSTRACT

A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention is directed generally to semiconductorinterconnections and a method for forming a semiconductor interconnect,such as a via or a contact, having an enlarged recess on its topsurface.

[0003] 2. Description of the Background

[0004] It is well known in the semiconductor art to use interconnects,known as vias and contacts, to connect an upper conductor of current,such as metal or polysilicon, through a dielectric layer to a lowerconductor of current. A via is an electrical connection between twometal layers, and a contact, in contrast, is an electrical connectionbetween anything other than two metal layers, such as between metal andsilicon. Vias and contacts are used extensively in very large scaleintegrated circuits, with an average circuit containing 16 million viasand contacts.

[0005] Vias and contacts are formed by an opening in a dielectric layerand a conductor within the opening. Directional deposition methods, suchas evaporation and sputtering, are often used to deposit the conductorwithin the opening. Such methods, however, often provide poor stepcoverage and only a thin conductive layer on the vertical wall of theopening. Thin layers are often not sufficient to provide good electricalcontact between the upper and lower conductors, and result in a highresistance and a propensity for electromigration failures.

[0006] The problem of poor step coverage is exaggerated as the size ofopening shrinks, and the aspect ratio increases. As the diameter of anopening approaches one micron, the aspect ratio typically approaches 1to 1. To reliably obtain good electrical connection, the opening isusually partially or entirely filled with a conductor, known as a“plug”.

[0007] Prior art methods for forming a plug typically include taperingthe top edge of the opening, followed by the formation of the plug inthe opening, and concluding with a hydrofluoric acid bath. The taperingof the top edge is often accomplished with a sputter etch, and thepurpose was to increase the surface area of the plug formed within theopening. The acid bath is used to clean the top surface of thedielectric layer, but it also dissolves some of the material at theinterface between the plug and the dielectric layer, creating a smallrecess several hundred Angstroms deep around the top edge of the plug.

[0008] The prior art methods have several shortcomings, such as poormetal coverage over the interconnect due to the small recess, whichoften contains impurities that increase the contact resistance, andwhich may develop into a latent defect. The latent defect may take theform of erosion of a top level conductor deposited on the recess, andcan be triggered if contaminants in the recess are exposed to moisturein a subsequent processing step. In addition, residuals left on thesurface of the wafer after the plug is formed may cause shorts betweenconductors on the wafer surface. Those residuals are often not removedby the hydrofluoric acid bath used in the prior art. Furthermore, when asputter etch is used to taper the corners of the opening, particlessputtered from the top edge of the opening end up in the bottom of theopening. These are particles of the dielectric layer, so they are notgood conductors of current, and they increase the contact resistance atthe bottom of the opening. Additionally, silicon regions are often thelower conductor of an interconnect, and it is well known that sputteringdamages and causes leakage in silicon. As a result, the prior artmethods either risk damaging the silicon regions, or require severaladditional process steps to provide a protective coating on siliconprior to the sputtering, and to remove the protective coating after thesputtering.

[0009] Defects occur in about 1 in every 100 million contacts. Since theaverage semiconductor device contains about 16 million contacts, adefect may be expected in more than one in every seven devices. Thedefects may be a latent defect caused by contamination in the recess,poor contact or adhesion at the top of the connection, poor contact atthe bottom of the connection caused, for example, by dielectric materialpresent from the sputtering step, or damage to a silicon region at thebottom of the opening.

[0010] Thus, the need exists for an improved method of forming aconnection having reduced contact resistance, improved contact adhesion,and decreased susceptibility to latent defects.

SUMMARY OF THE INVENTION

[0011] The present invention is directed generally to a method offorming a connection in an integrated circuit. The method includes thestep of depositing a lower conductor. A dielectric layer is deposited onthe lower conductor, with the dielectric layer having a lower surfaceadjacent to the lower conductor, and having an upper surface oppositethe lower conductor. An opening extending between the upper surface andthe lower surface of the dielectric layer is formed. A conductive plugis deposited within the opening. The plug has an upper surface proximatethe upper surface of the dielectric layer. An edge of the upper surfaceis adjacent to the dielectric layer. A recess is formed proximate theedge of the upper surface. The recess extends into both the plug and thedielectric layer. Finally, an upper conductor is deposited on the uppersurface of the dielectric layer and the upper surface of the plug.

[0012] The connection formed by the method of the invention is locatedwithin a dielectric layer of an integrated circuit, and is locatedbetween an upper conductor and a lower conductor. A conductive plug islocated within the opening, with the plug having an upper surfaceproximate the upper conductor, and an upper edge where the upper surfaceis adjacent to the dielectric layer. A recess is located proximate theupper edge of the plug. The recess extends into both the plug and thedielectric layer.

[0013] The invention solves the above-mentioned shortcomings in theprior art by cleaning the recess of impurities, thereby reducing therisk of a latent defect. Furthermore, at the same time that the recessis formed, the edge of the upper surface may be tapered therebyincreasing the surface area of the plug, increasing the adhesion by anupper conductor and decreasing the contact resistance. Finally, theinvention eliminates the need for sputtering the dielectric layer priorto the formation of the plug, thereby eliminating a source of dielectricmaterial in the bottom of the opening, and eliminating a potentialsource of damage to the lower conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein:

[0015] FIGS. 1-3 and 5-8 are cross sectional views of an integratedcircuit at successive steps in a method of fabricating an interconnectaccording to an embodiment of the invention;

[0016]FIG. 4 illustrates an alternative embodiment; and

[0017]FIG. 9 illustrates a system in which the present invention may beemployed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] It is to be understood that the figures have been simplified toillustrate only those aspects of an interconnect which are relevant, andsome of the dimensions have been exaggerated to convey a clearunderstanding of the present invention, while eliminating, for thepurpose of clarity, some elements normally found in an interconnect.Those of ordinary skill in the art will recognize that other elementsare required to produce an interconnect. However, because such elementsand process steps are well known in the art, and because they do notfurther aid in the understanding of the present invention, a discussionof such elements is not provided herein.

[0019]FIG. 1 is a cross-sectional view of a dielectric layer 2, asemiconductor layer 4, and an interface 6 between the dielectric layer 2and the semiconductor layer 4. The dielectric layer 2 may be of anydielectric material, and in the described embodiment it isboro-phospho-silicate glass oxide (“BPSG oxide”). A lower conductor 8 islocated in the semiconductor layer 2 adjacent to the interface 6, andmay be any conductor of current, such as a doped semiconductor or ametal. In the described embodiment, the lower conductor 8 is an n+ dopedsemiconductor. The lower conductor 8 is patterned to form conductivepaths as is known in the art. The dielectric layer 2, semiconductorlayer 4, interface 6, and lower conductor 8 form a portion of anintegrated circuit 10.

[0020]FIG. 2 is a cross-sectional view of the integrated circuit 10after an opening 12 has been created in the dielectric layer 2. Theopening 12 is defined by an inner wall 14 and extends from a top surface16 of the dielectric layer 2 to the lower conductor 8. The formation ofsuch an opening in a dielectric layer is well known in the prior art.For example, an anisotropic etch in a reactive ion etch (“RIE”) reactor,using CF₄+CHF₃ at between 10° C. and 40° C. may be used. Many othermethods of forming an opening are known, such as using a combination ofisotropic and anisotropic etches to create sloped side walls in adielectric layer.

[0021]FIG. 3 is a cross-sectional view of the integrated circuit 10after the deposition of a plug layer 20, which substantially fills theopening 12. Tungsten is preferred as the material for the plug layer 20because it is easily deposited using a chemical vapor deposition (“CVD”)process. Any conductor of current, however, may form the material forthe plug layer 20. Because tungsten does not readily adhere to oxides,which comprise the dielectric layer 2 in the preferred embodiment, a“glue” layer 22 is preferably deposited before the plug layer 20. In thepreferred embodiment titanium is used as the glue layer 22 because itadheres well to oxides and it consumes silicon dioxide, forming titaniumsilicide which has a low resistance. The silicon dioxide may remain atthe bottom 18 of the opening 12 from previous process steps, and if itis not removed, it will increase the contact resistance between a plug,described below, and the lower conductor 8.

[0022] Titanium may be deposited, for example, by using a chemical vapordeposition (“CVD”) process, preferably using a titanium-chloridechemistry, such as titanium and CFCl₃. Alternatively, titanium may besputtered directly onto the opening 12. Because sputtered titanium oftenresults in shadowing, a columniator may be utilized to provide a moreuniform distribution.

[0023] An alternative glue layer is titanium silicide, deposited by aCVD process. Titanium silicide CVD produces a conformal layer oftitanium silicide, yielding uniform metal layers along the vertical andhorizontal surfaces in and around the opening 12. The titanium silicideCVD process uses titanium tetrachloride in conjunction with titanium andsilicon gasses to produce the layer of titanium silicide. Titaniumsilicide, however, does not consume silicon dioxide as titanium does.

[0024] In addition to the glue layer 22, a barrier layer 24 is used inthe preferred embodiment because tungsten reacts with silicon to cause“worm holes” in the silicon. Worm holes result in small voids in thesilicon surface where the silicon has migrated into the tungsten, andthey increase the contact resistance and can cause leakage in diodesbuilt in the silicon substrate. As a result, the barrier layer 24 ispreferably used to separate the tungsten layer 20 from any form ofsilicon, such as a doped silicon substrate. When both a glue layer 22and a barrier layer 24 are used, both the glue layer 22 and the barrierlayer 24 may coat the bottom 18 and the walls 14 of the opening 12, asshown in FIG. 3.

[0025]FIG. 4 shows an alternative embodiment wherein the glue layer 22is deposited only on the bottom 18 of the opening 12, so that it willconsume any silicon dioxide present on the lower conductor 8. Thebarrier layer 24, however, is deposited on both the walls 14 and thebottom 18 of the opening 12. The preferred barrier layer 24, titaniumnitride, is suitable as both a “barrier” and a “glue”, and is depositedon top of the glue layer 22, to act as a barrier between tungsten andsilicon, and on the walls 14 to act as a glue layer. Titanium nitridereadily adheres to the titanium/titanium silicide glue layer 22, to thetungsten plug layer 20, and to the dielectric layer 2. It also forms aneffective barrier between the tungsten plug 26 and silicon, and isconformal and easily deposited by a CVD process. The titanium nitridemay also be deposited by annealing titanium in the presence of nitrogenor ammonia.

[0026] Regardless of the manner in which titanium nitride is deposited,an annealing step follows the deposition of the glue layer 22,preferably either immediately after the glue layer 22 is deposited, orafter the barrier layer 24 is deposited. The annealing step is necessaryfor the titanium, which preferably comprises the glue layer 22, toeffectively consume silicon dioxide.

[0027] The glue and barrier layers 22 and 24, of course, are preferablynot used when the plug 26 does not react adversely with any othermaterials in the opening 12, and when the plug 26 adequately adheres tothe wall 14 and bottom 18 of the opening. In fact, the glue and barrierlayers 22 and 24 are not required to utilize the invention, but they areused in the preferred embodiment. A layer of titanium may always beused, however, to consume silicon dioxide from the bottom 18 of theopening 12.

[0028]FIG. 5 shows a cross-sectional view of the integrated circuit 10after portions of the plug layer 20, glue layer 22, and barrier layer 24have been removed, leaving a plug 26 having a top surface 28 and an edge29. The edge 29 of the plug 26 is defined generally by the glue andbarrier layers 22 and 24. The portions of the plug layer 20, glue layer22, and barrier layer 24 may be removed, for example, by a dry etchprocess using a chlorine-based gas is used, such as chlorine gas, CCl₄,or HCl. Preferably, however, a chemical-mechanical polish (“CMP”), asdescribed in U.S. Pat. No. 5,224,534 (“the '534 Patent”) issued to Yu etal., assigned to Micron Technology, Inc. and incorporated herein byreference, may be used to remove the top layer of tungsten and leave thetop surface 28 of the plug 26 even with the top surface 16 of thedielectric layer 2.

[0029]FIG. 6 shows the integrated circuit 10 after being subjected to acleaning step. The surface of the integrated circuit 10 is cleaned, forexample, by a bath of hydrofluoric acid which cleans the surface 16 ofthe dielectric layer 2 and opens up a small recess 30 in the glue andbarrier layers 22 and 24 around the edge 29 of the plug 26. The recess30 has a generally rectangular cross-section, is typically between 1,000and 2,000 Angstroms deep, typically about 1,000 Angstroms wide, and willoften contain impurities. As discussed above, if the impurities remainin the recess 30 they may develop into a latent defect which mayultimately cause a failure of the device. As described in the '534Patent, the CMP process may also form a recess 30 at the edge 29 of theplug 26, without the use of a hydrofluoric acid bath.

[0030] Following the cleaning step, an “etchback” step is preferablyperformed which removes material from the top surface 28 of the plug 26so that the plug 26 is between about 1,000 to 2,000 Angstroms below thetop surface 16 of the dielectric layer 2. The etchback is to compensatefor the different etch rates of tungsten and BPSG oxide, in anticipationof an etch step described below with respect to FIG. 7. The depth of theetchback is chosen so that at the conclusion of the etch step, discussedbelow with respect to FIG. 7, the top surface 28 of the plug 26 and thetop surface 16 of the dielectric layer 2 are even. The etchback may beachieved, for example, through a dry etch of the plug 26.

[0031]FIG. 7 shows a cross section of the integrated circuit 10 after itis subjected to an etch step to clean and enlarge the recess 30. Afterthe recess 30 is enlarged it extends into the dielectric layer 2 and theplug 26. Many types of etches, such as facet etches and sputter etches,may be used to clean and enlarge the recess 30. It has been found,however, that superior results are achieved with a sputter etch using anargon plasma, with a pressure between five and fifty millitorr, a flowrate of between 10 and 100 standard cubic centimeters per minute(“sccm”) of argon gas, a plasma energy level of between 1.7 and 5.1watts per square centimeter of the target surface, and an angle between400 and 600 above horizontal. In the most preferred embodiment, thesputter etch angle is 580 above horizontal. The sputter etch typicallyincreases the width of the recess 30 from about 1,000 Angstroms tobetween about 2,000 Angstroms and 3,000 Angstroms, although the depth ofthe recess 30 is usually not significantly changed of course, bothlarger and smaller recesses 30 are possible, and the depth of the recessmay be changed to suit particular needs by, for example, altering thesputter etch angle. When the sputter etch increases the width of therecess 30, it tapers the top surface 28 of the plug 26, which increasesthe surface area of the plug 26, and it tapers the top surface 16 of thedielectric layer 2. The increased surface area of the plug 26 allows fora lower resistance contact and better adhesion with a subsequentlyapplied upper conductor. The tapered plug 26 and dielectric layer 2 alsoallow for very good step coverage over the recess 30 when a subsequentupper conductor layer is applied, as described below with respect toFIG. 8. The sputter etch also cleans the recess 30 of impurities andresidue remaining from previous process steps, further reducing thelikelihood of a latent defect. Furthermore, the sputter etch cleans thesurface of the integrated circuit 10 of impurities and removes residue,such as tungsten particles deposited during the formation of the plug26, which are often not removed in the cleaning step using hydrofluoricacid.

[0032] During the sputter etch step both the plug 26 and the dielectriclayer 2 are etched, but because tungsten sputters more slowly than BPSGoxide, the thickness of the plug 26 decreases at a slower rate than thethickness of the dielectric layer 2. For that reason, in the preferredembodiment the top surface 28 of the plug 26 is etched back about 1,000to 2,000 Angstroms below the top surface 16 of the dielectric layer 2prior to the etch step. As a result of the etchback of the plug 26, atthe conclusion of the sputter etch the top surface 28 of the plug 26 isapproximately even with the top surface 16 of the dielectric layer 2.

[0033]FIG. 8 is a cross-sectional view of the integrated circuit 10after a top conductor layer 32 has been applied to the top surface 16 ofthe dielectric layer 2 and the top surface 28 of the plug 26. The topconductor layer 32 fills the recess 30, taking advantage of theincreased surface area of the plug 26, and resulting in a lowerresistance contact and better contact adhesion. Good step coverage overthe recess 30 results from the tapered plug 26 and dielectric layer 2.The top conductor layer 32 may be any conductor of current, such asaluminum, titanium, copper, or polysilicon, and methods of deposition ofthe top conductor layer 32 are well known in the prior art, such as bysputtering and CVD. The top conductor layer 32 is patterned to formconductive paths as is known in the art.

[0034]FIG. 9 illustrates a system 34 in which the present invention maybe employed. The system is comprised of a solid state device, such asmemory device 36, in which connections of the type disclosed herein aremade. The memory device is under the control of a microprocessor 38which may be programmed to carry out particular functions as is known inthe art.

[0035] Those with ordinary skill in the art will recognize that manymodifications and variations of the present invention may beimplemented. For example, the recess 30 may be formed in a plug 26 anddielectric layer 2 without the presence of glue and barrier layers 22and 24. The foregoing description and the following claims are intendedto cover all such modifications and variations.

What is claimed is:
 1. A method of forming a connection in an integratedcircuit, comprising the steps of: depositing a lower conductor;depositing a dielectric layer on the lower conductor, the dielectriclayer having a lower surface adjacent to the lower conductor and havingan upper surface; forming an opening in the dielectric layer, theopening extending between the upper surface and the lower surface;depositing a conductive plug within the opening, the plug having anupper surface proximate the upper surface of the dielectric layer, theupper surface having an edge where the upper surface is adjacent to thedielectric layer; forming a recess proximate the edge of the uppersurface, the recess extending into both the plug and the dielectriclayer; and depositing an upper conductor on the upper surface of thedielectric layer and the upper surface of the plug.
 2. The method ofclaim 1 , wherein said step of depositing a conductive plug comprisesthe step of chemical vapor deposition of tungsten.
 3. The method ofclaim 1 , additionally comprising the steps of depositing a glue layerand depositing a barrier layer before said step of depositing aconductive plug.
 4. The method of claim 3 , wherein said step ofdepositing a glue layer comprises the step of depositing a titaniumlayer and the step of depositing a barrier layer comprises the step ofdepositing a titanium nitride layer.
 5. The method of claim 1 , whereinsaid step of forming a recess comprises the step of sputter etching. 6.The method of claim 5 , wherein said step of sputter etching comprisesthe step of sputter etching with an argon plasma.
 7. The method of claim6 , wherein said step of sputter etching comprises the step of sputteretching at a pressure between five and fifty millitorr of pressure. 8.The method of claim 6 , wherein said step of sputter etching comprisesthe step of sputter etching at an energy between 1.7 and 5.1 watts persquare centimeter.
 9. The method of claim 6 , wherein said step ofsputter etching comprises the step of sputter etching with a gas flowrate between 10 and 100 standard cubic centimeters per minute.
 10. Themethod of claim 6 , wherein said step of sputter etching comprises thestep of sputter etching at an angle between 40° and 60° abovehorizontal.
 11. The method of claim 6 , wherein the step of sputteretching comprises the step of sputter etching at an angle ofapproximately 58° above horizontal.
 12. The method of claim 1 , whereinthe step of forming a recess further comprises the step of tapering theedge of the upper surface and tapering the upper surface of thedielectric layer.
 13. The method of claim 1 , further comprising thestep of etching back the plug before said step of forming a recessextending into both the plug and the dielectric layer.
 14. A connectioncarried in a dielectric layer of an integrated circuit, located betweenan upper conductor and a lower conductor, comprising: a conductive pluglocated within the opening, said plug having an upper surface proximatethe upper conductor, said upper surface having an edge where said uppersurface is adjacent to the dielectric layer, and said plug having alower surface proximate the lower conductor of current; and a recess atsaid edge of said plug, and said recess extending into both said plugand said dielectric layer.
 15. The connection of claim 14 , wherein saidconductive plug comprises tungsten.
 16. The connection of claim 14 ,further comprising a glue layer and a barrier layer between thedielectric layer and said conductive plug.
 17. The connection of claim16 , wherein said glue layer comprises titanium and said barrier layercomprises titanium-nitride.
 18. The connection of claim 14 , whereinsaid recess includes a taper along said edge of said upper surface. 19.The connection of claim 14 , wherein the recess is between 1,000Angstroms and 2,000 Angstroms deep.
 20. The connection of claim 14 ,wherein the recess is between 1,000 Angstroms and 3,000 Angstroms wide.21. The connection of claim 14 , wherein the recess has a “v”cross-sectional shape.
 22. The connection of claim 14 , wherein theupper conductor comprises a metal and the lower conductor comprises asemiconductor.
 23. The connection of claim 14 , wherein the upperconductor comprises a metal and the lower conductor comprises a metal.24. The connection of claim 14 , wherein the upper conductor comprises asemiconductor and the lower conductor comprises a semiconductor.
 25. Theconnection of claim 14 , wherein the upper conductor comprises asemiconductor and the lower conductor comprises a metal.
 26. A system,comprising: a microprocessor; and a memory device in communication withsaid microprocessor, said memory device having a connection carried in adielectric layer thereof and located between an upper conductor and alower conductor, a conductive plug located within the opening, said plughaving an upper surface proximate the upper conductor, said uppersurface having an edge where said upper surface is adjacent to thedielectric layer, and said plug having a lower surface proximate thelower conductor of current, and a recess at said edge of said plug, andsaid recess extending into both said plug and said dielectric layer. 27.The system of claim 26 , wherein said memory device includes a dynamicrandom access memory.